Previous work, such as that described in U.S. Pat. No. 6,269,277 entitled “System And Method For Designing Integrated Circuits”, has demonstrated the ease with which a circuit design can be optimized against a critical parameter (also referred to as an “objective”) using geometric programming (GP) techniques. Here, each equation in a family of equations that describe the circuit's characteristics and/or behavior is expressed in monomial or posynomial form (which for purposes of this application includes convex form) as an equality or inequality in a computer readable format (e.g., in a text file). Equations may also be expressed in signomial form (or another analytical form) if the design process is targeted to a signomial problem solver (or another solver including a general-purpose numerical optimization solver).
Numeric values are plugged into the family of equations for a “scenario” of the circuit's operation that specifies its operating conditions (e.g., temperature, supply voltage, input voltage, pertinent manufacturing process parameters, input/output conditions, load conditions, switch settings, etc.) and desired functional characteristics (e.g., gain, bandwidth, etc.). Equation terms within the family of equations that specify transistor level netlist details (e.g., such as transistor gate dimensions, resistance values and capacitance values) are left as “unknowns” that need to be defined in order for the circuit to meet the objective (e.g., “minimized” power consumption or size) under the scenario.
The family of numerically enhanced equations is then provided to a signomial or geometric optimization problem solver or generic numerical optimization solver implemented on a computing system with program code. Execution of the optimization problem solving sequence returns specific numeric values for the transistor level unknowns that satisfy the objective (e.g., minimal power consumption or circuit size) for the desired number of scenarios. Thus, the solution provided by the optimization problem solver provides details sufficient to design a transistor level netlist for the circuit.
A problem however is that commercial applications demand that a circuit design meet certain behavioral characteristics over a large number of scenarios. As such, an optimization problem sequence must be undertaken across multiple scenarios in an effort to confirm the circuit's adaptability to varying conditions. Often times, because of the practical difficulties associated with optimization problem solving over large numbers of scenarios, one limits the number of scenarios over which the problem is solved. As a result, one or more of the original scenarios can be infeasible and a global transistor level definition for the circuit cannot be determined over the entire range of scenarios
Thus, a need exists for a circuit design process that utilizes optimization problem solving techniques to produce transistor level details for a circuit that “works” over a large number of different scenarios.
In the field of mathematics, “robust optimization” is an optimization approach that deals with uncertainty. Specifically, in order to deal with the uncertainty, different scenarios are solved that express numeric values across the uncertainty range. Also in the field of mathematics, a process known as an “active set method” partitions inequality constraints into two sets: an active set for immediate solution and an inactive set for subsequent solution. The inactive set of inequality constraints is ignored when the active set of inequality constraints is solved. Known prior art active set methods, however, do not: 1) express equalities in the set of constraints (i.e., only inequalities are used); or, 2) classify variables within the set of constraints as being unknown and scenario dependent.